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Author Topic: EPT 4 Channel 15MHz DSO scheduled for Sept 2016
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Post EPT 4 Channel 15MHz DSO scheduled for Sept 2016
on: June 17, 2016, 21:05
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We are still not complete with the EPT Digital Storage Oscilloscope (DSO). We will be calling the Oscilloscope Interface Board by its new name, EPT Digital Storage Oscilloscope. We have made progress, but still have a ways to go. The Verilog Project compiled and fit perfectly into the FPGA. The basic bugs between FPGA and PC software have been worked out. The UnoProLyzer software is taking data from the DSO board and displaying it on screen. But, the analog front end had to be redesigned.

The new schematic and layout for Version 2 is complete and currently under review, checking for errors. We should be ready to have the boards fabricated this week. Then, board build up will occur over the next weeks after that. During this time, we will start work on the Version 2 of the Verilog code. This version adds the I2C buses and other decode functionality. Once the V2 boards are assembled, we will do a board bring up check, then add the Verilog code. Debug the FPGA to PC software interface. Then we can get the UnoProLyzer software modifications complete and run the whole EPT DSO at the top rated speed. Next, we will need to debug triggering and display issues. At this point, we are still looking at another two months or more before boards are ready for shipping. We will keep you informed.

You can view a pdf of the debugging of the EPT DSO to this point http://www.earthpeopletechnology.com/wp-content/uploads/2015/03/DSO Hardware Verification PGA Channel Cycling and ADC Bipolar Input.pdf

EPT DSO FPGA and PC Software Debug

Debugging the EPT DSO V1 board has been performed using a Mixed Signal Oscilloscope. 16 digital signals can be monitored and displayed on the Oscilloscope. Also four channels of analog can be displayed as well.

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Single Board PCB with 24 I/O pins broken out to connectors for connections to DSO. There has been many cut traces and jumper wires added to the EPT DSO during debug.

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Probing the EPT Oscilloscope Int Board with Logic Analyzer and Oscilloscope to examine signals in real time.Internal FPGA signals are connected to FPGA pins which allows these signals to be displayed on the Oscilloscope.

This screen shot from the Oscilloscope shows the FPGA internal signals communicating with Memory and SPI blocks.

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FPGA Code is initiated by the UnoProLyzer Software. This software is also used to capture and display signals from the ADC.This is a screen shot from the UnoProLyzer Software. This shows the four channels being populated with data from ADC.

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The FPGA is correctly cycling through all four channels and storing the results of the ADC conversion correctly in its local memory.

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This verifies that the PGA and FPGA channel switching is occurring correctly. The issues that can be seen are the “glitches” (positive going pulses) that occur every few milliseconds. The height of these pulses does not seem to be correlated to fixed value. These will have to be investigated further.

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The next issue to notice is that the values are 0V, 0.6V, 0.8V and 1.0V. The EPT DSO board has fixed voltage dividers providing a test voltage for each of the four channels. From the oscilloscope screen shot, it can be seen that
•Channel 1 = 100mV
•Channel 2 = 200mV
•Channel 3 = 400mV
•Channel 4 = 600mV

The ADC converts these positive values into the upper half of the eight bit range of values. The ADC uses a reference voltage of 1.2V peak to peak. This means the Maximum Positive Voltage the ADC will correctly convert is 0.6V.

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So, the positive range of the ADC means that:
•0.0V = 128 counts from the ADC
•0.6V = 256 counts from the ADC

For the negative range on the ADC:
• -0.6V = 0 counts from the ADC

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The UnoProLyzer Software is set up for values from a 10 But ADC (the UnoProLogic2). This can be seen from the above code snippet with multiplying the sample “n” by 450 (This gives an offset of 450 pixels from the top most pixel. The resulting conditioned value will be subtracted from the bottom most pixel value before displaying the pixel value. This is a method to place the pixel correctly in the oscilloscope window). Then dividing by the total number of counts per ADC range (the old value of 1024 counts has not been changed from the UnoProLogic2's 10 bit ADC). This value should be 256.

So, a value of 128 will be displayed as 0.5V on the UnoProLyzer Oscilloscope window. The positive deflections from 128 will be displayed as increments from +0.5V up to +1.0Von the UnoProLyzer Oscilloscope window. This will be fixed in the next release of software.

Next issue to notice is the ADC is a true bipolar input. This means for the positive range of the ADC: 0.0V = 128 counts from the ADC 0.6V = 256 counts from the ADC For the negative range on the ADC: -0.6V = 0 counts from the ADC

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This is a problem because the PGA117 part is unipolar only. It only accepts and outputs signal from 0V to AVDD. So, this analog front end will never correctly display the output of the Op-Amp signal conditioners.

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The analog front end circuit must be changed to remove the PGA117 and redesign the Op-Amp circuit to the above circuit. The output of this circuit will feed directly into the ADC. This circuit was simulated and correctly output the +/- 40 volts down-converted to +/-0.6 volts.

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Redesigning the circuit to remove the PGA117 part will eliminate the ability of the circuit to select a single channel for input into the ADC. So, we need a hardware switching mechanism to select a channel. After searching through several analog multiplexor parts, it was determined that there is not a good cheap part to accomplish this switching at the analog signal level.

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So, it was determined that four separate 8 Bit High Speed ADC’s would be used with their output buses tied to 8 bit transceivers. The output of the transceivers will be connected to one eight bit bus that is connected to the FPGA. This scheme will allow the FPGA to select a channel by turning on the Output Enable signal of the selected channel. The multiplexing is done at the digital level.

This approach of using four separate 8 Bit ADCs will increase the cost of the overall board. However, the benefits are true 80MSamples per Second for each channel. So, each channel will have a bandwidth of 10-15MHz. Besides the increased cost of the board, the size of the board will grow to accommodate the extra IC’s. The new schematic and layout are complete. The design and layout are being reviewed at this time. The new layout is below.

See the EPT DSO V2 Schematic herehttp://www.earthpeopletechnology.com/wp-content/uploads/2015/03/ept_4ce6_do_u2_v2_20160523.pdf.

The new schematic and layout are complete. The design and layout are being reviewed at this time. The new layout is below.

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