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Author Topic: DSO 4 Channel 15 MHz Development Update Oct 2016 TOPIC CLOSED
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Post DSO 4 Channel 15 MHz Development Update Oct 2016
on: October 11, 2016, 17:02

I built up the first sample of the V2 DSO board and found a few minor problems such as incorrect footprints for a couple of passives. Unfortunately, the new footprints for the oscillators did not get correctly placed. So, the old incorrect footprints are on the V2 board. The board powers up Ok and debugging is under way. You can see my debug setup here:
Image
http://www.earthpeopletechnology.com/wp-content/uploads/2015/03/EPT_DSO_V2_Debug_Lab_Setup_001.jpg
Digital Multiplexor and Analog Conditioning Circuits
Great news, both the ADC digital multiplexor and analog signal conditioning circuits are working correctly. The DSO can now correctly convert both positive and negative signals and display them on each channel correctly. Here is the first view of a 100Hz 1V peak to peak signal at offset 0.0V:
Image
http://www.earthpeopletechnology.com/wp-content/uploads/2015/03/EPT_DSO_V2_Screen_Capture_Channel_2_with_1V_pk-pk_100Hz_signal_001.jpg
The zero point for the screen capture above is 0.7V. You can see the positive signal extends about +0.350V above the zero point and swigns -0.350V below the zero point. The digital potentiometers measure 1.6K Ohm by default at power up. I calculated the gain for both Op-Amps and the +/-0.350V is correct for a 1V input signal. You can see all four channels are displayed correctly.
Things to fix
The screen capture above was taken a couple of seconds after start up. When I leave the DSO to continue taking data, all four channels start to get crossed data between the channels. This means, the data is loosing sync with the indexing for the memory blocks. This problem could be either in the Verilog code or the C# code. I am looking into this problem now.
I need to exercise the I2C bus and find out what problems exist in this path. Once these problems are ironed out, I can set the gain to any one of 255 different levels.
I need to add code into both Verilog and C# to acheive the maximum sample speed of 80MHz.
I need to create multiple buffers in the Verilog code to allow longer periods of time to be stored before transmission to the C# code on the PC.

Coming Down the Home Stretch
So, none of these problems are show stoppers at this time. I don't believe there are any major changes to be made to the hardware. The Verilog and C# code need a good bit of work to complete. I am hopeful, these problems can be fixed over the next three weeks. Then, I can make the footprints fixes to the board. Then get the gerbers produced. Then, we can start assembling the boards. Unfortunately, we don't have enough money to get this round of the DSO boards factory assembled. So, we will have to build them by hand. We will do this build with a stencil and a reflow oven which will improve out throughput. But, hand placing 300 parts is time consuming. Once I have finished the code and testing, I will try to put together a schedule for delivery of boards.

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