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Author Topic: Olimexino compatible?
brucemelle-
n
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Post Re: Olimexino compatible?
on: May 31, 2013, 17:24
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I would actually [instead] suggest getting a Olimexino STM32 (available from mouser). It uses the Maple IDE. And also get an Arduino Due (also available from Mouser), both for development/verification of a product to work on the 'ino ARM platforms.
If you have the extra change laying around for...the slightly older Maple board itself is not quite as good a product (power limitations and a few others) and appears a bit languishing - new leaflabs hardware development appears stopped but verification with your product would be good.
However there still appears to be some Maple IDE development activity with people fixing bugs in and expanding it a bit - so I expect the open code may remain to support the existing Maple product line and Olimexino board - both still selling in unknown quantities.
I expect Arduino is committed to supporting the Due as the newer/next technology. On their Arduino specs-compare web page, the Due is listed right below the Uno.
FYI...Olimex also has a ARDUINO-COMPATIBLE GAMEDUINO-BASED EXTENSION SHIELD that has a FPGA on it. I think that target audience is different, however.
If you care to take this thread off the forum, feel free to use my email instead.

brucemelle-
n
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Posts: 14
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Post Re: Olimexino compatible?
on: June 1, 2013, 03:34
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Maybe it would be worth making the product targeted for the 'ino ARM market that can be software-loaded/jumper-set backward compatible to work with the Uno... Multiple products but really one PCB, maybe with the same components on it, or almost the same.
I really would like:
* [nearly] all the CPLD pins somehow available.
* easy connectivity of [nearly] all CPLD & ‘ino pins to a breadboard.
* There are a couple MCU board pin layouts out there: the Maple/Olimexino/Uno pre R-3, Uno R-3, and the Due. All have Eagle files available. If you build official shield pins as is on the Due, extras can be cut off when used on the Maple/Olimexino/Unos Rev x – just plan CPLD pinouts so the ones that get cut off are not critical. Put solder pads on the bottom layer of the CPLD board so a SMT pin header can be soldered on to connect into Maple/Olimexino’s 16 pin header. Also put solder pads on the bottom layer of the CPLD board so a SMT pin header can be soldered on to connect into the Due’s 36 pin header. The reason I request solder pads on the bottom layer is because I hope you then have room on the upper board plane to take all the CPLD & shield traces to a dual row of 40 0.1" pitch plated holes similar to http://users.ece.utexas.edu/~valvano/EE345L/Labs/Fall2011/LM3S1968soldering.pdf where that UofTexas professor then added pin headers - to nicely mount it onto a breadboard. To fit the dual row, make the PCB a trapezoid - a distinctive market attention-getter. Just give me the dual row of plated holes, I'll buy/mount the appropriate pin headers. Just keep the traces close to the same lengths & watch out for layout noise – flood as much as possible.
I know I'm not the only one with this kind of need, as a couple of EE professors I work with are currently looking for a student-friendly microprocessor w/CPLD/FPGA solution to use in their low level digital electronics classes at the large local community college. I don't know how far they have gotten in their decision process, probably too far to consider your product this round, but I hear they want each student to buy something affordable (MCU board , wire kit, breadboard, and CPLD/FPGA [board] with IDEs likely under $100 total). I assume other educational institutions also look at the market every couple years - with all the robotics classes/competitions currently being driven by 'duino and some other boards. CPLD and FPGA could have a big role as students develop/fail/redevelop/test their robots and other simulated embedded devices. For one course I took for fun, I simulated operation of a microwave oven and it was painful using an old slow MCU board with only a few pins available, programmed in Basic and a gazillion DIP logic chips on three breadboards. For the next course I bought, much to the professor's chagrin, the Olimexino, bought some SMT to DIP adapters for breadboard testing, and then designed/had manufactured a PCB that remained controlled by the Olimexino; that project needed little logic. This local community college is a 2yr feeder for Rochester Institute of Technology, The University of Rochester, and other NY State engineering schools. I hear more and more of the robotics students are choosing ARM-based boards. The market is there for a mature, friendly, inexpensive CPLD/FPGA board with a good reputation, but it could take a few years. I don't yet see someone meeting the CPLD/FPGA need in the market.

brucemelle-
n
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Posts: 14
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Post Re: Olimexino compatible?
on: June 3, 2013, 14:10
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I want you to succeed: a useful CPLD learning/classroom/hobbyist/experimentation/prototyping product that is priced appropriately for the user.

Few subjects: technical and marketing

1) After doing some more reading, I’m wondering…
• Should you use more than a 6 pin power shield header? I do not see other shields implement more; more pins will be in the way of some other ‘ino board components.
• Instead of the 10 pin shield header, shouldn't it be 8 pins like most other shields in the same location? Should that ‘ino connector’s AREF pin really be connected to the CPLD? Should that ‘ino connector’s GND pin really be connected to the CPLD? , Although I guess the two pins to the other side of AREF should be connected.
• Should you really connect either the TX or RX pin on the digital shield bank to the CPLD, in that it may interfere with USB programming of the ‘ino board?
• For the above points, I’m also comparing with the Amani GTX and Amani F2 boards.
2) I don’t fully understand your choice of using the MAX II instead of the MAX V. Explaining these things and selling your approach and product flexibility is always good on your site.
• MAX V have an internal oscillator (could you then eliminate the need for the $1.50 oscillator?) and MAX V are considerably cheaper for the same number of LEs, but you would then need a $cheap? 1.8V regulator (?) to supply core power? MAX V also seems to have a couple more features that I don’t understand how/when they can be useful. Would it run cooler too? But it also looks to run slower. Or is toasting a Max V CPLD easy & too high a risk for this market? Comparing 570LE 85° slowest models, I do see availability of the MAX V more limited in the $7.50 (mouser) 100TQFP (less than the MAX II at $13.30) – or do you have cheaper sources?
3) Why did you go with the expensive FT2232H mini-module? I would assume Altera’s USB Blaster circuitry (seems it has been decoded to use) or FTDI’s chip on your board would be cheaper. Again, explaining these things and selling your approach is always good on your site.
4) It seems like a number of the ‘ino CPLD/FPGA ‘rapid prototyping’ products have not been successful. My impression is based upon lack of copious posted successes/projects within the past couple years. Suggestions:
• Name your products something easy to remember and to search for, so only you are found with that name but you are also easily found found in many places by searching market terminology. ‘EPT cpld shield for ARM’ hits little at the moment, but is the market for the one product I’m looking for. EPT-570-AP-U2 is not a good name in the ‘ino shield marketplace. Use your chosen terminology and the products you work with a lot on your site.
• I would suggest you sponsor a local robotics group or work with a local college electronics dept – to supply & see how your evolving product line can help education, and they can help you debug/evolve the products.
• Smart manufacturers know that subsidizing development boards is good for long-term business. Student developers grow up to build embedded systems using the same brand. TI has learned in their pricing of their LaunchPad. Try to get backing and funding from Altera; their current evaluation products are not targeting the education marketplace (too expensive and not in conjunction with a well-known MCU board/platform).
• When the product is ready, try to get into some of the hobbyist online stores.
- Sparkfun.com
- Cutedigi.com
- Freetronics.com
- And others
• I’ve only seen your product in one place other than your site, and due to my forum posts elsewhere. Look for where and how your predecessors and competition show up on the Internet – and make sure projects using your board appear everywhere:
- Dangerousprototypes.com
- Hackaday.com
- Open7400 logic competition – get involved/supply some boards/sponsor some submissions
- http://www.youtube.com/watch?v=hOkBcKbx40Y
- http://www.youtube.com/watch?v=UWfGvjPJ-F8 is why I want to connect directly to a breadboard
- http://forums.netduino.com/index.php?/topic/4000-amani-gtx-netduino-plus/
- http://hackaday.com/2012/05/23/measuring-projectiles-with-openchronometer/
- http://stackoverflow.com/questions/15194206/seven-segment-multiplexing-on-basys2
- …and a lot more

EPT_User
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Posts: 20
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Post Re: Olimexino compatible?
on: June 3, 2013, 15:08
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Ok, I see what you saying about adding as much flexibility in access to the pins of the CPLD. I would prefer to create multiple CPLD/FPGA boards, one for each Due, Maple, and maybe a combo ARM/FPGA. The reason for this is I want to create specialized User Manuals for each board. I have a lot of experience with using development boards to produce projects for customers. The more general you make a user manual the longer it takes to understand the operation of the board. In this day and age of short cycle project times, anything that can be done to decrease the learning curve is of large value to the customer.
What do you think about creating an Arduino like IDE for the CPLD/FPGA devices? This would include a subset of the functionality that Verilog can do. The user creates a project in this environment then the compile/synthesize button would call the Quartus II mapping and layout tool.

brucemelle-
n
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Posts: 14
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Post Re: Olimexino compatible?
on: June 3, 2013, 18:22
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My gut feel/sense, not knowing the difficulty of Quartus II/Web IDE, is to use your supplied text libraries/text code inclusion for your board that have the 'ino & CPLD shield pins defined the way they are used in the Maple/Arduino Due IDEs and grouped appropriately considering your project development experience, and have me/the student developer, use the latest real Quartus II/WebIDE. I don't think I want to depend upon any small shield developer to maintain a special IDE that has to change as Quartus changes its product. I don’t want a board to be obsolete if the mfr is no longer around and Quartus has a major revision. Should I assume Quartus II/Web is friendlier than the tools offered by Xilinx or Lattice? I expect to have to learn/copy some VHDL and/or Verilog, like I’ve had to learn C. Don’t isolate me/students too much from concepts/what is needed in the real world, but then again don’t bury me like having to write in assembly language for a MCU. Ask yourself what a EE caliber student team new to MCUs and CPLD could best use when they have 1 semester to accomplish… search the web & youtube for “2012 ASEE Model Design Competition” and also consider a different EE digital course project where pairs of students develop working imbedded logic & interfaces for a typical microwave oven – keypad, simple display, logic/circuitry for lights, turntable, power tube, timing…. In 1/3 of a semester. Or a semester course with small teams developing the logic/power circuitry and PCB with all/most chips to create a usable file from a bare CCD mounted on a board under a lens (lots of logic & timing). ‘We’ offer these three courses. Courses like this get students a chunkable experience culminating in a success, which will lead to more successes. My personal need is not dissimilar except that I want to have my end-project communicate with a Windows PC application.
Could you target more custom manuals toward robotics, embedded systems, and separately for all the higher end audio/visual processing that some more experienced people are aiming for? That would best leverage your user's time and may get yourself into more student and hobbyist hands. You need to sell professors who search for materials that leverage student time and that will be there the following year. Sometimes you need to send an evaluation copy & provide some support when walls are hit. National Instruments does this but goes the other way with too expensive and complicated a product for students new to the technologies.
Isn’t FPGA adding another level of complexity and having to reload the program every time it is powered on? And cost for both chips needed?

EPT_User
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Post Re: Olimexino compatible?
on: June 4, 2013, 03:59
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The reason for the current design of the EPT-570-AP is the high speed USB chip (480 Mbps) on the FT2232H Mini Module. I wanted to create a board that can program the CPLD and provide a high speed communication path to the Windows PC. See this document http://www.earthpeopletechnology.com/wp-content/uploads/2013/03/EPT_USB_CPLD_DEV_SYS_FEATURES.pdf for details. The CPLD board was designed for two layers with ground fill on top and bottom. The high speed USB should be routed on a board with four layers and controlled impedance. Four layer boards are more expensive than two layers. So, the solution was to use an FT2232H Mini Module and a two layer base board. I do like the MAX V family, however, so does everybody else. This means its hard to keep these parts in stock. Using a MAX V part will definitely drive the cost up because of the need to go to a four layer board and integrate the FT2232H chip onto the board. Or I could add a +1.8V regulator but the cost still goes up. The internal oscillator is only good for 3.9 to 5.3 MHz. I need greater than 60 MHz to drive the high speed USB transfer library.
Check out this video to see the ability of the EPT-570-AP to transfer data at high speed. Please keep in mind this is a rough draft of the video intro. I am working a full video tutorial of the Analog Monitor project at the moment. http://www.earthpeopletechnology.com/wp-content/uploads/2013/06/Analog_Monitor_Draft_Intro.mp4

brucemelle-
n
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Posts: 14
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Post Re: Olimexino compatible?
on: June 4, 2013, 14:04
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I’m not knowledgeable enough to understand why (ignoring the off-board communications) the Max V would need a 4 layer board, and the internally faster with same core voltage Max II would not. I was trying to save your cost by questioning.
I read/viewed your links. I see the analog sampling application but do not yet see the widespread need for anywhere near 480Mbps.
I'm surprised the 'ino families, especially the Uno, can generate/accept a stream of digital data anywhere the speed you are talking. Isn't the data stream also going through both two 2 layer boards [designed for lower speeds] and the unshielded shield headers to get to the FT2232H mini-module? I obviously don't yet understand the real need to run digital communication external to the physical CPLD chip that fast. For my project, when I send a signal to the CPLD, I'm just looking for logic-resulting output from another pin in the 10-40ns range and figured the high frequency need is internal to the CPLD chip. When I did my ‘microwave’ project and from what I understand in the robotics arena, they don't need that fast an external speed. For the camera project I was part of, the timing signals and data moved seemed to need about the same responsiveness as my current project; noise from the hanging wires and breadboards students have during development greatly limit digital data transfer speed.
It appears that you are wanting/targeting the board for a higher-end need and EE developer than what I’ve been thinking, and it would cost measurably less with a slower USB CPLD programming&data port approach. I know 4-layer boards are considerably more expensive. I don’t know the cost of the USB Blaster circuitry Altera uses on its 2/4 layer eval boards or whether it can be used to talk data with Windows apps. I assume FTDI has less expensive albeit slower chips that can readily be put on a 2-layer board (or run them slower), thus saving much of the cost of the separate FTDI module.
At some price point, hobbyists will buy a shield just to try it. And if they have success, more will buy. The hobbyists and student projects I see don’t, I believe, need such high speed/cost but they like to see data communication with the module like your video. Couldn’t the analog sampling have been less frequent; eyes/brain can’t even perceive more than ~15 numbers/second change. What projects controlled by a ‘ino ARM MCU (forget the Uno) and a CPLD needs to move that much data that quickly to/from the PC, other than real-time audio/video? I would think a different higher-end board would be applicable for A/V need.

EPT_User
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Post Re: Olimexino compatible?
on: June 4, 2013, 20:16
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You are absolutely correct! The Max V is a superior chip to the Max II. I could just drop it into the EPT-570-AP and add a +1.8V regulator and everything would work just fine. No need to go to a four layer board. Let me give you an example of why I am using 66MHz clock. In robotics, we typically use SPI sensors to send data to the Arduino. If I put the Master SPI bus into the CPLD, I need to produce an SPI clock at the typical rate of 4MHz. This means my internal clock has to be a minimum of two times the output clock rate. I need two positive edges internally to produce one positive output edge and one negative output edge. So, I need an internal clock of minimum 8 MHz. If I want to talk to fast sensors and move data quickly, the SPI clock needs to be 8MHz and I need an internal clock of 16MHz. Let's take the slave approach, make the CPLD the slave SPI device. Now, I need to sample the incoming SPI clock at 4 times per SPI clock period. I have to do it at four times because twice per period could sample at exactly the falling or rising edge of the SPI clock and the CPLD would never see a clock. So, my internal clock now has to be 4 * 8MHz = 32MHz.
Let me give you an example of why the USB high speed (480 Mbps) is very useful. The Arduino requires two clocks per instruction for the PORT write. It can send data at 4M Bytes per second! I agree with you that streaming the ADC outputs to PC monitor is not an effective use of this bandwidth. Typically in computer/data systems, we use a burst mode. That is we store up a set of data over a period of time, then send the data set as quickly as possible to another computer.This is how TCP/IP works. Let me tell you about the next project I am working on, The Arduino High Speed Oscilloscope. As you know, the oscilloscope gets a trigger and stores up a collection of samples for a period of time. Then, it bursts this data to the screen for display. After the burst, it resets its trigger and waits for the next trigger. The faster it can burst data and get back to waiting for the next trigger, the more fluid the oscilloscope looks.

May I ask you what your price point for a CPLD board would be? After our discussions here on the forum, would you be in the market for a single 2 layer board with an FTDI FT2232D, Altera 5M570, and all the I/O's brought out to 0.1" through hole pads around the perimeter of the board? I could not populate the through hole pads and let the user provide their own connectors. This would keep the board pretty cheap.

brucemelle-
n
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Posts: 14
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Post Re: Olimexino compatible?
on: June 5, 2013, 07:47
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Getting a couple small things out of the way…
You say the Max V is much better, but after looking, isn’t it ~½ the speed of the Max II?
If you say the Max V and Max II in 100TQFP are the same pinouts except for core power voltage, then I’d lay down the pads for an appropriate voltage regulator and lay a 0ΩR to get 3.3V to it until the less expensive Max V are more available. Verify both models&faster Max II versions.
BTW – make the CPLD shield’s USB connector type match the ‘ino board being used. I’m not sure, but I think the Due uses a different USB end than the Olimexino STM32 and Maple.
Now to the meat…
The Due CPLD shield board needs to talk with all the Due’s pins that make sense to connect, including the Due’s 18x2 header and two new 8x1 headers. Similar for the Maple/Olimexino STM32 CPLD shield with their 8x2 header and older style Uno headers. And on the non-USB end, as suggested in earlier posts, I would want to see two rows, spaced 0.1”, of 20 through-hole pads with 0.1” pitch (you have just enough space without widening the shield), for 40 well selected CPLD&’ino&power traces to ultimately feed a breadboard. The row closest the board edge would be centered .26” from the edge of the board and the 2nd row would be .36” – so if the user mounts a PEC20SBBN or similar in the 1st row, it should insert 5.84mm into the breadboard, and a PEC20SGBN or similar in the 2nd row should insert 5.54mm – board edge into the breadboard’s center groove, which seems to be .1” deep & .1” wide. Applicable RA header tails need to be ≥.2” to solder through the board, and the RA header heads need to be ≥~3mm beyond the edge of the board.
Can you run good traces through the Due’s 18x2 header, or does the 18x2 header need to be surface mounted on the bottom layer and not extend to the upper layer of the shield to get traces beyond, toward the edge? The Due layout seems to make getting a lot of pin signals to the edge of the shield difficult.
What happens to board cost if you make it L or trapezoidal shaped to make that 40 into all useable CPLD/’ino/power pins in just two rows? Or a second side with a dual row of through-hole pads for the signals that don't make the top 40? I think putting two pairs of rows would be more desirable/friendly than having a single row around the perimeter of the board. Appx. cost per area of 2 layer board? Maybe just 40 pins will be enough to directly take to a breadboard as long as the others can be gotten to via jumper wire.
It is sounding like the Due board will be more expensive to make than the Maple/Olimexino STM32 version, for several reasons.
Let me know if you want me to sketch diagrams of what I’m thinking can be done.
The pair of rows to breadboard would be a marketing draw to your board, even if the user needs to separately purchase & solder the pins. “With a little solder & the $5 pin headers, you can plug the shield with the ‘ino on it, directly into your breadboard.” You may get some buyers drawn to your product for that feature alone.
I would look for an ARM ‘ino oriented Altera 570LE CPLD shield, RoHS compliant, w/USB capable programming & data transfer circuitry (I’m not expecting high burst speed for this price; more than tens of Mbs has little extra value to me ) (no USB cable included), and if the relevant maple/olimexino STM32/Due 16/32 pin headers need to be surface mount on the shield, have them placed because soldering alignment could be problematic by user, through-hole pads for the user to separately purchase/install the breadboard headers I mentioned, should they separately want them, at a price point of $34.19 in single qty for the Maple version and $39.19 for the Due version, w/$5.80 priority mail small flat rate box shipping+any applicable tax. Not quite as much as you are currently pricing because CPLD does not yet have quite the ring that FPGA and Microprocessor do and many will not yet see the benefits (until they hear from others/Internet). Offer Due 18x2 or Maple 8x2 headers to solder on ($2), breadboard headers to solder on ($5), and an applicable usb cable ($4) all to hopefully stuff in the same priority mail box with the shield. User can elsewhere buy a ‘ino board for another $30-50, appropriate MCU board power brick $10, and a breadboard and extensive jumper wire kit $10, all, including domestic shipping, hopefully for little over $100.

EPT_User
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Post Re: Olimexino compatible?
on: June 5, 2013, 21:33
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My bad, I meant to say the Max V is better for the EPT-570-AP application. It can handle the 66 MHz oscillator without any problems. So, you believe the price point should be $34, Full Speed USB (12 Mbps), Altera 570 CPLD and can handle multiple connector configurations. I would like to see your diagram if you have time to produce it. I will contact you via your email so we can exchange ideas in private. Yes, it is unfortunate that students are more familiar with FPGA's than CPLD's. PLD's predate FPGA's by 10 years. I don't know why they are attracted to FPGA's if they're not storing large amounts of data, then the FPGA is overkill.

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