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Author Topic: pinout map & pin availability
brucemelle-
n
Newbie
Posts: 14
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Post pinout map & pin availability
on: May 29, 2013, 04:32
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I’ve scanned the manual and am in the process of reading more thoroughly, anticipating purchase….My first in the world of CPLD/FPGA.
Do you have a 1 page pinout map cross-referencing MAX II EPM570T100 Function/Bank/pin# (and/or whatever the Quartus II IDE uses) and the Arduino Uno bank/pin# (like, for ex, PC2 or PB5 and what the Arduino/Maple IDE uses)? Or is that what the EPT Active Transfer Library is about?
Should I assume I can get 16-19 more than the ~24 pins advertised if I access them through the pair of 13x2 connectors when the FT2232H Mini Module is not mounted? Are the J1 & J2 connector pins written on your board so I can tell pin locations? And are they included on any pinout map cross-reference? Have you thought about a relatively simple connector/ribbon cable/connector so that the 16 MAX II-connected pins on J2 can be reoriented and connected unobtrusively to a string of 8 pins spanning the center of a std breadboard? Something inexpensive that could coexist with or replace something like a Duinomite-Shield & Duinomite-TBA to get the shield [and applicable/available J1&J2] pins to a std breadboard? At least that could get us close to 40 of the 76 I/O pins touted on the MAX II EPM570T100.

brucemelle-
n
Newbie
Posts: 14
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Post Re: pinout map & pin availability
on: May 31, 2013, 19:06
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Sorry, posted reply in wrong thread.

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